The need for high-performance, low-power, and low-cost systems for network
transport and wireless communications is driving silicon technology toward higher
speed, higher integration, and more functionality. Further more, this integration of
RF and analog mixed-signal circuits into high-performance digital signal-
processing (DSP) systems must be done with minimum cost overhead to be
commercially viable. While some analog and RF designs have been attempted in
mainstream digital-only complimentary metal-oxide semiconductor (CMOS)
technologies, almost all designs that require stringent RF performance use bipolar
or semiconductor technology. Silicon integrated circuit (IC) products that, at
present, require modern bipolar or BiCMOS silicon technology in wired
application space include the essential optical network (SONET) and synchronous
digital hierarchy (SDH) operating at 10 Gb/s and higher.
The viability of a mixed digital/analog. RF chip depends on the cost of making the
silicon with the required elements; in practice, it must approximate the cost of the
CMOS wafer, Cycle times for processing the wafer should not significantly exceed
cycle times for a digital CMOS wafer. Yields of the SOC chip must be similar to
those of a multi-chip implementation. Much of this article will examine process
techniques that achieve the objectives of low cost, rapid cycle time, and solid yield.
1 comments:
I think BiCMOS devices offer many advantages where high load current sinking and sourcing is required. The high current gain of the NPN transistor greatly improves the output drive capability of a conventional CMOS device.
Compared to CMOS, BiCMOS’s reduced dependence on capacitive load and the multiple circuit and I/Os configurations possible greatly enhance design flexibility and can lead to reduced cycle time
IC Design
Post a Comment